panel string | configuration_key string | algorithm string | adaptation string | source_configuration_id string | model string | workload string | configuration_level string | gpu_count int64 | actor_micro_batch int64 | vllm_gpu_memory_utilization float64 | parameter_offload bool | free_cache_engine bool | total_training_steps int64 | observed_state string | eligible_processes int64 | planned_processes int64 | missing_processes int64 | other_failure_processes int64 | memory_failure_processes int64 | failure_modes string | max_completed_peak_mib float64 | mean_completed_peak_mib float64 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
hardware_transfer | amd-3676c66cad477bbb | grpo | lora | cfg-00e028aa49d34e64 | microsoft/Phi-4-mini-instruct | gsm8k | joint | 2 | 16 | 0.7 | false | true | 1 | above_margin | 3 | 3 | 0 | 0 | 0 | null | 64,756 | 64,211 |
hardware_transfer | amd-58689244cc3e554e | grpo | lora | cfg-072bd7669d20f8fa | microsoft/Phi-4-mini-instruct | math | c3 | 4 | 16 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 62,744 | 62,682.3 |
hardware_transfer | amd-7a4aa814cdd7fc71 | grpo | lora | cfg-09d34ea9e791de94 | Qwen/Qwen2.5-3B-Instruct | gsm8k | reservation_only | 2 | 8 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 57,692 | 57,637.3 |
hardware_transfer | amd-10dc40d3ee084759 | grpo | lora | cfg-0f540d3f6fe4661b | microsoft/Phi-4-mini-instruct | math | c2 | 2 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 55,540 | 55,473.3 |
hardware_transfer | amd-3323c146ee1cddc9 | grpo | lora | cfg-0f8a31ef7ac4c551 | microsoft/Phi-4-mini-instruct | math | c1 | 2 | 4 | 0.45 | true | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 44,637 | 44,296.3 |
hardware_transfer | amd-07714872b6cf4c4e | grpo | lora | cfg-1432bb8a4d9c3b8c | microsoft/Phi-4-mini-instruct | math | c4 | 4 | 16 | 0.8 | false | true | 1 | memory_failure | 3 | 3 | 0 | 0 | 3 | generation_wakeup_oom;update_weights_oom | null | null |
hardware_transfer | amd-3f2c004121459594 | grpo | lora | cfg-14d47144a7cbb833 | microsoft/Phi-4-mini-instruct | gsm8k | base | 2 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 53,972 | 53,757.3 |
hardware_transfer | amd-16aa91c382fcee55 | grpo | lora | cfg-17e69bcf1b041bd9 | microsoft/Phi-4-mini-instruct | gsm8k | c3 | 4 | 16 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 57,722 | 57,664 |
hardware_transfer | amd-db208f246a3c4daf | grpo | lora | cfg-18edbed17d1a0c2e | Qwen/Qwen2.5-3B-Instruct | math | safe_margin | 2 | 2 | 0.35 | true | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 37,367 | 37,092 |
hardware_transfer | amd-2942e2d84a06a471 | grpo | lora | cfg-191bdf2aa4d09de2 | microsoft/Phi-4-mini-instruct | math | base | 2 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 55,496 | 55,461 |
hardware_transfer | amd-7c663a31f02a7c0e | grpo | lora | cfg-211b6fafd167a310 | microsoft/Phi-4-mini-instruct | math | actor_only | 2 | 16 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 60,420 | 60,354 |
hardware_transfer | amd-31ddc8f9592d9050 | grpo | lora | cfg-2afbe250af9cd3e1 | ibm-granite/granite-3.3-2b-instruct | math | c3 | 4 | 16 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 54,764 | 54,581 |
hardware_transfer | amd-4f8670d8bc94a368 | grpo | lora | cfg-301e4dae7048c6ec | microsoft/Phi-4-mini-instruct | gsm8k | c2 | 4 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 51,034 | 50,095 |
hardware_transfer | amd-95d1b5ecf5287987 | grpo | lora | cfg-30e348e68aa5fb5c | Qwen/Qwen2.5-3B-Instruct | math | near_boundary | 2 | 16 | 0.65 | false | false | 1 | memory_failure | 3 | 3 | 0 | 0 | 3 | update_actor_oom;update_weights_oom | null | null |
hardware_transfer | amd-b0db192cb313b102 | grpo | lora | cfg-30f98456fdb322c1 | Qwen/Qwen2.5-3B-Instruct | math | c2 | 2 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 52,291 | 52,106.3 |
hardware_transfer | amd-efa37088bbe2696a | grpo | lora | cfg-32977d5aa42a41cb | ibm-granite/granite-3.3-2b-instruct | math | c5 | 2 | 32 | 0.85 | false | true | 1 | memory_failure | 3 | 3 | 0 | 0 | 3 | generation_wakeup_oom;update_weights_oom | null | null |
hardware_transfer | amd-95ab18c5ee8fa418 | grpo | lora | cfg-338d9224eb9d2f3a | Qwen/Qwen2.5-3B-Instruct | gsm8k | c2 | 2 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 51,342 | 51,208 |
hardware_transfer | amd-a228d8b325a815e1 | grpo | lora | cfg-352f4dbc55fbcd3c | Qwen/Qwen2.5-3B-Instruct | gsm8k | c5 | 2 | 32 | 0.85 | false | true | 1 | memory_failure | 3 | 3 | 0 | 0 | 3 | generation_wakeup_oom;update_weights_oom | null | null |
hardware_transfer | amd-c2aa8d9dbf7bd299 | grpo | lora | cfg-371ae37408089efe | microsoft/Phi-4-mini-instruct | math | c2 | 4 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 51,585 | 51,566.3 |
hardware_transfer | amd-9680c83e3c59777b | grpo | lora | cfg-399f6b038d6f65f9 | Qwen/Qwen2.5-3B-Instruct | gsm8k | c2 | 4 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 48,636 | 48,162.3 |
hardware_transfer | amd-2ca307101ddfa774 | grpo | lora | cfg-3b9787f775169f3d | ibm-granite/granite-3.3-2b-instruct | math | actor_only | 2 | 16 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 51,501 | 51,285.7 |
hardware_transfer | amd-bc36784076bf5976 | grpo | lora | cfg-3c86a11fdb8455cb | microsoft/Phi-4-mini-instruct | gsm8k | c5 | 2 | 32 | 0.85 | false | true | 1 | unresolved | 2 | 3 | 0 | 1 | 2 | generation_wakeup_oom | null | null |
hardware_transfer | amd-db2d88aac405ec72 | grpo | lora | cfg-3ca7715d60421fe4 | microsoft/Phi-4-mini-instruct | math | joint | 2 | 16 | 0.7 | false | true | 1 | memory_failure | 3 | 3 | 0 | 0 | 3 | generation_wakeup_oom;update_weights_oom | null | null |
hardware_transfer | amd-410b15e6c95b4909 | grpo | lora | cfg-3f0f48a3c570a0c8 | Qwen/Qwen2.5-3B-Instruct | math | c0 | 2 | 1 | 0.3 | true | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 31,154 | 30,889.3 |
hardware_transfer | amd-5b5cf2b323b2a85f | grpo | lora | cfg-3fb18b33cd9f8bcf | Qwen/Qwen2.5-3B-Instruct | math | near_boundary | 2 | 16 | 0.65 | false | true | 1 | above_margin | 3 | 3 | 0 | 0 | 0 | null | 64,788 | 64,753.7 |
hardware_transfer | amd-31dac0b7c4eb7aa7 | grpo | lora | cfg-402f13fde534d758 | Qwen/Qwen2.5-3B-Instruct | gsm8k | actor_only | 2 | 16 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 54,685 | 54,484 |
hardware_transfer | amd-aba6d1da0a9c7f3c | grpo | lora | cfg-419301d6d3eea82b | Qwen/Qwen2.5-3B-Instruct | gsm8k | safe_margin | 2 | 1 | 0.3 | true | false | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 41,366 | 41,119.3 |
hardware_transfer | amd-2206ce9d2c7ab26b | grpo | lora | cfg-445e1547e9317cd0 | ibm-granite/granite-3.3-2b-instruct | gsm8k | base | 2 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 49,582 | 49,344.3 |
hardware_transfer | amd-cd828bf6bf3d3751 | grpo | lora | cfg-44b1b60788cfb061 | Qwen/Qwen2.5-3B-Instruct | gsm8k | safe_margin | 2 | 1 | 0.3 | true | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 29,000 | 28,912 |
hardware_transfer | amd-624145edbc91703d | grpo | lora | cfg-4e0b53e75324e5f8 | Qwen/Qwen2.5-3B-Instruct | gsm8k | near_boundary | 2 | 16 | 0.65 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 58,828 | 58,660 |
hardware_transfer | amd-b26b51d5745e7038 | grpo | lora | cfg-5047dff55c13e55f | Qwen/Qwen2.5-3B-Instruct | gsm8k | base | 2 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 51,399 | 51,225.3 |
hardware_transfer | amd-f7931ebca5cf43f3 | grpo | lora | cfg-5244d13eac3116ad | Qwen/Qwen2.5-3B-Instruct | gsm8k | c0 | 2 | 1 | 0.3 | true | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 29,579 | 29,189.3 |
hardware_transfer | amd-6db1179b0ce02cdc | grpo | lora | cfg-55811d23c5144bb7 | Qwen/Qwen2.5-3B-Instruct | math | c4 | 2 | 16 | 0.8 | false | true | 1 | memory_failure | 3 | 3 | 0 | 0 | 3 | generation_wakeup_oom | null | null |
hardware_transfer | amd-7d0e120c76c6677c | grpo | lora | cfg-57f3e6381e2a814a | microsoft/Phi-4-mini-instruct | gsm8k | actor_only | 2 | 16 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 58,020 | 57,547.3 |
hardware_transfer | amd-e240b3480ce8542e | grpo | lora | cfg-5839ccf95c2c1722 | Qwen/Qwen2.5-3B-Instruct | gsm8k | c4 | 2 | 16 | 0.8 | false | true | 1 | memory_failure | 3 | 3 | 0 | 0 | 3 | generation_wakeup_oom;update_weights_oom | null | null |
hardware_transfer | amd-2e3bce1d496ae6aa | grpo | lora | cfg-584e6c6664859977 | ibm-granite/granite-3.3-2b-instruct | gsm8k | actor_only | 2 | 16 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 50,968 | 50,706 |
hardware_transfer | amd-c228404d62439c3d | grpo | lora | cfg-5c14e44760909675 | Qwen/Qwen2.5-1.5B-Instruct | math | near_boundary | 2 | 16 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 59,017 | 58,938 |
hardware_transfer | amd-d89e11c1db30d91c | grpo | lora | cfg-5ff9621270e710ed | microsoft/Phi-4-mini-instruct | gsm8k | c4 | 4 | 16 | 0.8 | false | true | 1 | above_margin | 3 | 3 | 0 | 0 | 0 | null | 65,497 | 64,649.7 |
hardware_transfer | amd-0d9dfdf3635c8357 | grpo | lora | cfg-62f371a80968a0ba | Qwen/Qwen2.5-3B-Instruct | math | c1 | 2 | 4 | 0.45 | true | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 40,717 | 40,621.7 |
hardware_transfer | amd-0f111e00e982fa73 | grpo | lora | cfg-6a4562db98b38d6f | ibm-granite/granite-3.3-2b-instruct | gsm8k | c4 | 2 | 16 | 0.8 | false | true | 1 | above_margin | 3 | 3 | 0 | 0 | 0 | null | 64,082 | 63,851.7 |
hardware_transfer | amd-97c36f5b27a63ec8 | grpo | lora | cfg-714c540f76d9525d | Qwen/Qwen2.5-3B-Instruct | math | c3 | 4 | 16 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 59,570 | 59,446.3 |
hardware_transfer | amd-319586df8cb983ad | grpo | lora | cfg-71b33248b3cb3190 | ibm-granite/granite-3.3-2b-instruct | math | joint | 2 | 16 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 57,784 | 57,676.7 |
hardware_transfer | amd-702dace60b98e62b | grpo | lora | cfg-73c06764ba28a56b | ibm-granite/granite-3.3-2b-instruct | gsm8k | c3 | 2 | 16 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 57,623 | 57,371.7 |
hardware_transfer | amd-a6f8c442329499cc | grpo | lora | cfg-75662a6552e74f29 | ibm-granite/granite-3.3-2b-instruct | math | base | 2 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 49,442 | 49,378.3 |
hardware_transfer | amd-9e2e15f277fffe36 | grpo | lora | cfg-78c440d3891ddbc2 | Qwen/Qwen2.5-3B-Instruct | gsm8k | c4 | 4 | 16 | 0.8 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 62,639 | 62,593 |
hardware_transfer | amd-8a629db678e853a2 | grpo | lora | cfg-7a9a974958c57abc | Qwen/Qwen2.5-3B-Instruct | gsm8k | c3 | 2 | 16 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 61,106 | 60,897.3 |
hardware_transfer | amd-4c003e96f4a40527 | grpo | lora | cfg-7ee75feb0b09675f | Qwen/Qwen2.5-3B-Instruct | math | actor_only | 2 | 16 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 55,971 | 55,899 |
hardware_transfer | amd-cee9bcdb405f0c9c | grpo | lora | cfg-835067f7405e89a2 | ibm-granite/granite-3.3-2b-instruct | math | c3 | 2 | 16 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 57,673 | 57,639.7 |
hardware_transfer | amd-ac8a1ce2d05b8157 | grpo | lora | cfg-8a39420e5b484230 | microsoft/Phi-4-mini-instruct | math | reservation_only | 2 | 8 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 62,189 | 62,156 |
hardware_transfer | amd-eade522db41fb9ae | grpo | lora | cfg-8b7eb5281a925727 | ibm-granite/granite-3.3-2b-instruct | gsm8k | joint | 2 | 16 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 57,132 | 57,021.3 |
hardware_transfer | amd-0fb5b9b1ad50c1b7 | grpo | lora | cfg-8bd7050cd7f49e78 | microsoft/Phi-4-mini-instruct | gsm8k | c0 | 2 | 1 | 0.3 | true | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 35,589 | 34,980.3 |
hardware_transfer | amd-c55449d2a3ce2003 | grpo | lora | cfg-966f5804dc918967 | microsoft/Phi-4-mini-instruct | gsm8k | c4 | 2 | 16 | 0.8 | false | true | 1 | memory_failure | 3 | 3 | 0 | 0 | 3 | generation_wakeup_oom | null | null |
hardware_transfer | amd-41118f3abadb1a03 | grpo | lora | cfg-96ccf395b84393f7 | microsoft/Phi-4-mini-instruct | gsm8k | c2 | 2 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 55,038 | 54,148.7 |
hardware_transfer | amd-59a6bce242dfad16 | grpo | lora | cfg-9758870c0a0b4d69 | ibm-granite/granite-3.3-2b-instruct | math | c2 | 4 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 46,538 | 46,404.3 |
hardware_transfer | amd-e6738cdc8f14edf2 | grpo | lora | cfg-997a5dca920f4fb3 | Qwen/Qwen2.5-1.5B-Instruct | gsm8k | near_boundary | 2 | 16 | 0.7 | false | false | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 60,914 | 60,779.7 |
hardware_transfer | amd-c4c173bd73fc3a93 | grpo | lora | cfg-9f624ec22aa3dde0 | ibm-granite/granite-3.3-2b-instruct | math | c4 | 4 | 16 | 0.8 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 61,423 | 61,250.3 |
hardware_transfer | amd-dbaabe25ccc3db3b | grpo | lora | cfg-a188f9742074d270 | Qwen/Qwen2.5-3B-Instruct | gsm8k | near_boundary | 2 | 16 | 0.65 | false | false | 1 | above_margin | 3 | 3 | 0 | 0 | 0 | null | 65,074 | 64,932.3 |
hardware_transfer | amd-996a3920c206da4c | grpo | lora | cfg-a23a9ffc1f670139 | Qwen/Qwen2.5-3B-Instruct | math | c4 | 4 | 16 | 0.8 | false | true | 1 | above_margin | 3 | 3 | 0 | 0 | 0 | null | 65,499 | 65,495 |
hardware_transfer | amd-2ddef87b4d4f33f0 | grpo | lora | cfg-a3987314cb2f9f12 | microsoft/Phi-4-mini-instruct | math | c3 | 2 | 16 | 0.7 | false | true | 1 | memory_failure | 3 | 3 | 0 | 0 | 3 | generation_wakeup_oom | null | null |
hardware_transfer | amd-90f806956c6ba08f | grpo | lora | cfg-b1aeb72d4434b30d | microsoft/Phi-4-mini-instruct | gsm8k | reservation_only | 2 | 8 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 60,560 | 60,396.3 |
hardware_transfer | amd-8e04d7f20af81c6f | grpo | lora | cfg-b3fe40f61c5686ea | Qwen/Qwen2.5-1.5B-Instruct | math | near_boundary | 2 | 16 | 0.7 | false | false | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 63,425 | 62,877 |
hardware_transfer | amd-4ab62abdfa77b6bd | grpo | lora | cfg-b5352215babfeba6 | ibm-granite/granite-3.3-2b-instruct | math | c2 | 2 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 49,780 | 49,493.3 |
hardware_transfer | amd-bc00117c458b5d5d | grpo | lora | cfg-b56fb353c2f2fa3e | ibm-granite/granite-3.3-2b-instruct | math | c0 | 2 | 1 | 0.3 | true | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 28,614 | 28,360.3 |
hardware_transfer | amd-8e27f29e45ad0fb3 | grpo | lora | cfg-b5912aa6ea40b7fd | Qwen/Qwen2.5-3B-Instruct | math | base | 2 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 52,279 | 51,977.3 |
hardware_transfer | amd-c0364521aa0318de | grpo | lora | cfg-b68e9036992511d4 | Qwen/Qwen2.5-3B-Instruct | math | safe_margin | 2 | 2 | 0.35 | true | false | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 49,879 | 49,647 |
hardware_transfer | amd-75ad17324769e2b3 | grpo | lora | cfg-b7a35495ef8f0eb3 | Qwen/Qwen2.5-3B-Instruct | math | reservation_only | 2 | 8 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 58,886 | 58,598.3 |
hardware_transfer | amd-6466d4338e50b0f8 | grpo | lora | cfg-b8dd70ab682c13b2 | microsoft/Phi-4-mini-instruct | gsm8k | c1 | 2 | 4 | 0.45 | true | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 43,530 | 42,746 |
hardware_transfer | amd-4b92cc3197922be7 | grpo | lora | cfg-b8e90bd69c9744ea | ibm-granite/granite-3.3-2b-instruct | gsm8k | c2 | 4 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 46,230 | 46,099 |
hardware_transfer | amd-7e9226094b3a9bb6 | grpo | lora | cfg-c0605c1607caa079 | microsoft/Phi-4-mini-instruct | gsm8k | c3 | 2 | 16 | 0.7 | false | true | 1 | above_margin | 3 | 3 | 0 | 0 | 0 | null | 63,800 | 63,493.3 |
hardware_transfer | amd-139f7166b78a0a4f | grpo | lora | cfg-c2a8e6e8e140e109 | ibm-granite/granite-3.3-2b-instruct | gsm8k | c3 | 4 | 16 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 53,967 | 53,816 |
hardware_transfer | amd-aa09bb07a2afafa9 | grpo | lora | cfg-c2d27e8a89945048 | Qwen/Qwen2.5-3B-Instruct | gsm8k | joint | 2 | 16 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 61,178 | 60,860.7 |
hardware_transfer | amd-93c89359554f263d | grpo | lora | cfg-ca5490162c750c31 | Qwen/Qwen2.5-1.5B-Instruct | gsm8k | near_boundary | 2 | 16 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 57,395 | 57,303 |
hardware_transfer | amd-706ad7c152f967e2 | grpo | lora | cfg-cad8341dbbff10ba | Qwen/Qwen2.5-3B-Instruct | math | c5 | 2 | 32 | 0.85 | false | true | 1 | memory_failure | 3 | 3 | 0 | 0 | 3 | generation_wakeup_oom | null | null |
hardware_transfer | amd-59193ddd7363e2a8 | grpo | lora | cfg-cc2c35944156e5d4 | Qwen/Qwen2.5-3B-Instruct | gsm8k | c3 | 4 | 16 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 56,189 | 55,959 |
hardware_transfer | amd-f66257c3a7de06cf | grpo | lora | cfg-cc900fb7731c3f49 | microsoft/Phi-4-mini-instruct | math | c5 | 2 | 32 | 0.85 | false | true | 1 | memory_failure | 3 | 3 | 0 | 0 | 3 | generation_wakeup_oom;update_weights_oom | null | null |
hardware_transfer | amd-32d9f2b919bd63b2 | grpo | lora | cfg-cd3974595f9db882 | Qwen/Qwen2.5-3B-Instruct | gsm8k | c1 | 2 | 4 | 0.45 | true | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 39,863 | 39,850.3 |
hardware_transfer | amd-7db81e22afb3d04a | grpo | lora | cfg-d02503f8c9804a2d | ibm-granite/granite-3.3-2b-instruct | math | c4 | 2 | 16 | 0.8 | false | true | 1 | above_margin | 3 | 3 | 0 | 0 | 0 | null | 64,377 | 64,311 |
hardware_transfer | amd-24d583809fda82b1 | grpo | lora | cfg-d138048feeb8fe5d | microsoft/Phi-4-mini-instruct | math | c4 | 2 | 16 | 0.8 | false | true | 1 | memory_failure | 3 | 3 | 0 | 0 | 3 | generation_wakeup_oom;update_weights_oom | null | null |
hardware_transfer | amd-c4f9ec399c5617ad | grpo | lora | cfg-d4a213515805a9a7 | ibm-granite/granite-3.3-2b-instruct | gsm8k | c1 | 2 | 4 | 0.45 | true | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 38,448 | 38,268 |
hardware_transfer | amd-91cfeefed71df992 | grpo | lora | cfg-e2763ffc8afa3602 | ibm-granite/granite-3.3-2b-instruct | gsm8k | reservation_only | 2 | 8 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 56,033 | 55,815 |
hardware_transfer | amd-211b84c6cb8b5347 | grpo | lora | cfg-e2a205be8efba055 | microsoft/Phi-4-mini-instruct | math | c0 | 2 | 1 | 0.3 | true | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 37,642 | 37,535 |
hardware_transfer | amd-6af25cea86aba881 | grpo | lora | cfg-e8893b12558f51dd | ibm-granite/granite-3.3-2b-instruct | gsm8k | c5 | 2 | 32 | 0.85 | false | true | 1 | memory_failure | 3 | 3 | 0 | 0 | 3 | generation_wakeup_oom | null | null |
hardware_transfer | amd-80aca72cfd88de52 | grpo | lora | cfg-ef2331208f38fbaf | Qwen/Qwen2.5-3B-Instruct | math | joint | 2 | 16 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 62,766 | 62,708 |
hardware_transfer | amd-5f12edcf0010e0ce | grpo | lora | cfg-f009e9e3891c06f4 | Qwen/Qwen2.5-3B-Instruct | math | c3 | 2 | 16 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 62,445 | 62,426.7 |
hardware_transfer | amd-0130ef84798da33e | grpo | lora | cfg-f03e4e98c682240e | Qwen/Qwen2.5-3B-Instruct | math | c2 | 4 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 48,897 | 48,868.3 |
hardware_transfer | amd-1179d8822324c980 | grpo | lora | cfg-f439d2dd90137a80 | ibm-granite/granite-3.3-2b-instruct | gsm8k | c4 | 4 | 16 | 0.8 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 60,483 | 60,321.3 |
hardware_transfer | amd-43432b4d4cb0c7b3 | grpo | lora | cfg-f989b39cd682f07b | ibm-granite/granite-3.3-2b-instruct | math | reservation_only | 2 | 8 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 55,932 | 55,906.3 |
hardware_transfer | amd-863089f4586ab352 | grpo | lora | cfg-fbe1c0422f98cb38 | ibm-granite/granite-3.3-2b-instruct | gsm8k | c2 | 2 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 49,374 | 49,126.3 |
hardware_transfer | amd-a1e1493969108180 | grpo | lora | cfg-fd4d4789145230df | ibm-granite/granite-3.3-2b-instruct | math | c1 | 2 | 4 | 0.45 | true | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 38,250 | 38,132 |
hardware_transfer | amd-a9fe8a0a3475948b | grpo | lora | cfg-fd5bb0db68b0dae3 | ibm-granite/granite-3.3-2b-instruct | gsm8k | c0 | 2 | 1 | 0.3 | true | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 28,190 | 28,129.3 |
larger_models | amd-1357c30c5c7f243f | grpo | lora | cr-mistral-7b-math-c3-4gpu | mistralai/Mistral-7B-Instruct-v0.3 | math | c3 | 4 | 16 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 60,936 | 60,897 |
larger_models | amd-08589e8a12d1faa3 | grpo | lora | cr-mistral-7b-math-c3-2gpu | mistralai/Mistral-7B-Instruct-v0.3 | math | c3 | 2 | 16 | 0.7 | false | true | 1 | memory_failure | 3 | 3 | 0 | 0 | 3 | generation_wakeup_oom | null | null |
larger_models | amd-e7037dac094c2364 | grpo | lora | cr-mistral-7b-gsm8k-c3-4gpu | mistralai/Mistral-7B-Instruct-v0.3 | gsm8k | c3 | 4 | 16 | 0.7 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 60,920 | 60,892 |
larger_models | amd-d0e8d84e34fe568f | grpo | lora | cr-mistral-7b-gsm8k-c3-2gpu | mistralai/Mistral-7B-Instruct-v0.3 | gsm8k | c3 | 2 | 16 | 0.7 | false | true | 1 | memory_failure | 3 | 3 | 0 | 0 | 3 | generation_wakeup_oom | null | null |
larger_models | amd-ac93f889b5805c53 | grpo | lora | cr-mistral-7b-math-c2-2gpu | mistralai/Mistral-7B-Instruct-v0.3 | math | c2 | 2 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 59,631 | 59,597 |
larger_models | amd-a438947d12ad6fd1 | grpo | lora | cr-mistral-7b-math-c2-4gpu | mistralai/Mistral-7B-Instruct-v0.3 | math | c2 | 4 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 54,407 | 54,385 |
larger_models | amd-de7cb9dbda0404d0 | grpo | lora | cr-qwen25-7b-math-c1-2gpu | Qwen/Qwen2.5-7B-Instruct | math | c1 | 2 | 4 | 0.45 | true | true | 1 | above_margin | 3 | 3 | 0 | 0 | 0 | null | 64,746 | 64,604.3 |
larger_models | amd-d918158425cd57fe | grpo | lora | cr-qwen25-7b-math-c1-4gpu | Qwen/Qwen2.5-7B-Instruct | math | c1 | 4 | 4 | 0.45 | true | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 42,620 | 42,573.3 |
larger_models | amd-e27e4a5f61f12c83 | grpo | lora | cr-qwen25-7b-gsm8k-c2-4gpu | Qwen/Qwen2.5-7B-Instruct | gsm8k | c2 | 4 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 53,415 | 53,398.3 |
larger_models | amd-d8ae40fb976bc965 | grpo | lora | cr-qwen25-7b-gsm8k-c2-2gpu | Qwen/Qwen2.5-7B-Instruct | gsm8k | c2 | 2 | 8 | 0.6 | false | true | 1 | within_margin | 3 | 3 | 0 | 0 | 0 | null | 59,832 | 59,812.3 |
RLVRAMBench — Electronics submission
This is the dataset accompanying Memory Feasibility in Colocated Language-Model Reinforcement Learning: A Failure-Aware Measurement Study, prepared for the MDPI Electronics revision on 23 October 2026.
Submission version: electronics-submission-2026-10-23-r2. This version is
published on main and pinned by the same tag. Dataset DOI:
10.57967/hf/10780.
Earlier releases remain in the repository history and releases/.
- Main manuscript
- Scientific supplement
- Point-by-point reviewer response
- Editable TeX source ZIP
- Matching reproduction code
- Release manifest and archive hashes
- Submission data dictionary
- Reconstruction guide
Authors: Ondřej Kobza and Jan Šedivý, Czech Institute of Informatics, Robotics and Cybernetics, Czech Technical University in Prague. Author ORCIDs: Kobza, Šedivý.
What the dataset measures
RLVRAMBench measures GPU-memory feasibility when language-model generation and reinforcement-learning updates share devices. It retains successful, memory-failing, and ineligible executions. It provides stage measurements, controlled changes to execution settings, repeated configuration labels, frozen prediction tasks, and raw evidence. It does not measure model intelligence, convergence, or full-training quality.
The main experiments use synchronous LoRA-GRPO with VERL/vLLM on A100-40GB GPUs. Follow-ups add full-parameter 1.5B/3B actors, reservation and state-release sweeps, iteration costs, native LLMem validation, and an MI250X replication. The MI250X panel includes PPO with a full-parameter critic and changes hardware and software together; it is not an isolated hardware comparison.
Submission cohorts
The views above expose separate experimental units. Do not sum their rows as independent experiments.
| Cohort | Coverage and interpretation |
|---|---|
| Historical transfer benchmark | 52 tasks, 400 queries reusing 94 distinct targets |
| Independent A100 offload controls | 144 runs; 48 three-seed configurations: 36 within margin, 12 memory failures |
| A100 adaptation and no-KL controls | 108 formal runs: 106 within margin, 2 ineligible |
| A100 reservation sweep | 144 runs: 111 within margin, 11 above margin, 21 memory failures, 1 ineligible |
| A100 state-release sweep | 36 runs: 17 within margin, 6 above margin, 12 memory failures, 1 ineligible |
| A100 iteration costs | 24 runs, all within margin; 20 measured updates per run |
| Native LLMem validation | 24 prediction/measurement pairs in the supported native training setting |
| MI250X | 462 planned slots: 363 completions, 98 memory failures, 1 ineligible outcome; 154 configurations |
| DeepSpeed comparison | Recorded estimator calls and decisions on the same 400 benchmark queries |
The default view contains the 154 MI250X configurations, with panel
identifying the five substudies. Its A100 replay has 79 agreements among
89 resolved configurations, plus one unresolved configuration.
The unresolved Phi-4-mini/GSM8K c5 setting still exposes its two diagnosed OOMs.
The MI250X ledger records 510 started jobs and 511 executions, including
one Slurm restart. Pilots and unstarted submissions are separately identified.
Outcome rules and units
Memory is the maximum used memory on any one allocated device, in MiB, not a sum across devices. Completed-run peaks require successful completion and valid measurement evidence. An observed peak from a failed run is not its counterfactual completed memory demand.
| Label | Meaning |
|---|---|
within_margin |
All three eligible repetitions complete below or at the operating limit |
above_margin |
All three complete; at least one exceeds the operating limit |
memory_failure |
All three repetitions are eligible; at least one has a diagnosed device-memory failure |
unresolved |
Fewer than three eligible repetitions; known adverse observations remain visible |
The operating limit is capacity minus 2,048 MiB: 38,912 MiB for the A100 devices and 63,472 MiB for MI250X GCDs. This is a declared operating convention, not a probability guarantee. Per-run status vocabularies differ between historical collectors; see the data dictionaries. Missing values are missing evidence or inapplicable quantities, not zero memory.
Load a view
The direct Hub-loading interface is tested with Python 3.11,
datasets==5.1.0 and huggingface_hub==2.2.0. Install these from
dataset-client-requirements.txt in a separate reader environment. Older
clients such as datasets==2.12.0 ignore the card's configuration mapping
and may try to combine unrelated audit JSON files. The frozen raw-analysis
environment is documented separately in the reproduction guide.
python -m pip install -r dataset-client-requirements.txt
from datasets import load_dataset
configurations = load_dataset(
"kobzaond/RLVRAMBench",
"mi250x_configurations",
revision="electronics-submission-2026-10-23-r2",
split="measured",
)
Other views retain controls, historical transfer tasks, A100 follow-ups,
MI250X raw-derived trials, scheduler accounting, and estimator comparisons.
Use the configuration selector above or the inventory in
verification/dataset-views.json.
Raw evidence and reproduction
All four required raw-evidence archives are available under releases/:
RLVRAMBench-review-artifact-submission-20260917-b0018d0.tar.zst: historical measurements, admission/estimation, and replications.RLVRAMBench-offload-raw-20261022.tar.zst: independent offload controls, frozen source, and allocation accounting.electronics-full-20261021-a53af63.tar.zst: the four A100 follow-up panels, development attempts, native LLMem, and their frozen execution sources.RLVRAMBench-mi250x-raw-20261022.tar.zst: MI250X logs, device maps, memory/phase traces, submissions, and amendments.
Each archive has a SHA-256 sidecar. release.json records archive hashes,
coverage, and the code revision. MANIFEST.sha256 covers the submission
files. The reproduction guide separates raw reconstruction from replay of
already derived tables. No new GPU experiments are needed to reproduce the
released analyses. Verification reports describe author-performed checks;
they do not claim external replication.
The electronics_revision_2026_10/ folder is retained as an earlier curated
snapshot. The root-level paths and version tag above define this submission.
Historical IEEE PDFs remain archived; the linked MDPI PDFs are the current
submission documents.
Evaluation contract and limitations
Transfer queries expose source evidence and target settings. Target outcomes are public for audit but must not be read when producing predictions for that task. Independent screening and evaluation seeds remain distinct. Report failure approvals, above-margin approvals, useful approvals, and coverage together; aggregate accuracy alone is insufficient.
Measurements depend on the specified stack, device capacity, model, workload, state-release behavior, and requested duration. The longest runs cover 100 steps; the additional MI250X duration panel covers 40. The evidence does not establish frontier-scale feasibility, multi-node scaling, behavior on other engines or accelerators, or full-schedule convergence. The native LLMem and out-of-scope DeepSpeed component comparisons have different purposes. See the paper for scope and attribution limits.
License and citation
Original benchmark code, measurements, and documentation use the MIT license. Third-party material retains its original terms; see RIGHTS.md. Model weights and optimizer checkpoints are excluded. Source datasets and model identifiers are provenance, not a relicensing of upstream assets.
Use CITATION.cff, the dataset DOI, and the version tag when citing this release. The companion manuscript is a journal submission; no acceptance or publication status is implied.
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